Current large-scale computing systems include computer system components, such as multiple processors and memory banks, to perform various computer functions and applications. Data processing on such computing systems generally requires a large quantity of data transfers between the multiple processors and memory banks. System clocks are used to synchronize the data transfers between the multiple processors and memory banks. Due to data congestion and complexities associated with the system clocks, the multiple processors, and many memory banks, significant effort is made to manage such computing systems.
Many such computing systems often include a maintenance processor to maintain the system operations and functional integrity of computer systems components, such as the multiple processors and memory banks. A maintenance processor generally implements maintenance and/or utility functions for testing system operations and computer system components for functional integrity. A maintenance processor can check or reset various system operations such as date, time, and alarm status information. System configuration and network configuration parameters may be modified or tested with a maintenance processor.
Computer system components can also be tested and debugged with a maintenance processor. For example, a maintenance processor can test a memory bank by writing test data to the memory bank, reading the test data from the memory bank, and then comparing the written test data to the read test data. If the written test data matches the read test data, then the memory bank is deemed to be functional. Otherwise, if the written test data does not match the read test data, then the memory bank is non-functional. The maintenance processor typically records and reports the write/read test data comparison results.
In certain applications, a maintenance processor is programmed to reinitialize or shut down a computer system and thereby reset the processors and/or memory banks. A maintenance processor may also need to reinitialize memory components such as static random access memory (SRAM) or register arrays. One approach for reinitializing memory components with a maintenance processor uses a test operating mode that disables the system clocks. Computer functions and applications are delayed until the system clocks are enabled. Due to these delays, overall computer system performance is, of course, hindered.
An alternative approach to the foregoing allows a maintenance processor to access memory components dynamically. That is, the clock signal to the memory components remains enabled while the access occurs. This approach, however, requires additional logic, design time, software development time, and test development time. For example, the additional logic used for intermittent dynamic access may impact the target operating frequency of the system clock by inserting additional logic in critical timing paths. This may lengthen design cycles since these critical timing paths must be optimized. Also, these additions may lead to unforeseen software and testing problems.
Accordingly, it would be desirable to provide a manner for addressing the aforementioned and other shortcomings of the prior art. The present invention fulfills these and other needs, and provides a system and method for dynamically accessing memory components during normal system operation.